1. Field of the Invention
The present invention relates to a cache system for a computer system, and more particularly to a cache system and a control method therefor which is designed to access at high speed to a memory system when in a cache miss.
2. Description of the Prior Art
FIG. 1 is a block diagram of the conventional cache system, in which reference numeral 1 designates a CPU, 2 designates a cache, both the CPU and cache carrying out signal transmitting-receiving with each other through a bidirectional CPU-cache signal line L1, 3 designates a memory system which is connected to the CPU 1 through a connection line L2, a system bus SB, a connection lines L3, a CPU-system bus interface 4, and a connection line L4, and to the cache 2 through a connection line L2, a system bus SB, a connection line L5, a cache system bus interface 5 and a connection line L6.
In such construction, the CPU 1 gives a cache enabling signal to the cache 2 through the CPU-cache signal line L1 to thereby decide use or non-use of the cache 2.
When the CPU 1 puts the cache enabling signal in a notenable state so as not to use the cache 2, the CPU 1 accesses the memory system 3 through the connection line L4, CPU-system bus interface 4, connection line L3, system bus SB and connection line L2 (the course is called the "route I"), thereby reading and writing data. In this case, the CPU 1 serves as a bus master.
When the CPU 1 uses the cache 2 by putting the cache enabling signal in an enable state and the corresponding data exists in the cache 2 (cash hit), the CPU 1 reads the data from the cache 2 at high speed through the CPU-cache signal line L1, in which the CPU 1 also is the bus master.
When the CPU 1 uses the cache 2 and the corresponding data does not exist therein (cache miss) the CPU 1 accesses the memory system 3 through the CPU-cache signal line L1, cache 2, connection line L6, cache-system bus interface 5, connection line L5, system bus SB and connection line L2 (the course is called the "route II"), thereby reading and writing the data. In this case, the cache 2 serves as the bus master after the cache miss.
FIG. 2 is a structural view explanatory in detail of connection of signal lines between the cache 2 and the system bus SB.
As shown in the same drawing, at the CPU-cache signal line L1, connection lines L6 and L5, and system bus SB, address signals S1a, S6a, S5a and SBa, data signals S1b, S6b, S5b and SBb, and control signals S1c, S6c, S5c and SBc are transferred in the direction of the arrows in FIG. 2.
In the conventional cache system, constructed as the above-mentioned, the CPU 1 reads the data from the memory system 3 through different routes I and II respectively when the cache 2 is not used and the cache miss occurs.
A signal arrival time from the memory system 3 to the CPU 1 at the routes I and II, when the pass times for the CPU system bus interface 4 and the cache-system bus interface 5 are assumed to be about equal, the arrival time through the route II delays by a pass time for the cache 2. Therefore, a designer for the memory system 3 should design in consideration of the following matters.
For example, the memory system being very slow in access time in comparison with the CPU 1 and cache 2 must transmit to the CPU 1 (or the cache 2) a ready signal for indicating the data has been stably written in or ready to be read out. Next, explanation will be given on when the memory system 3 outputs the ready signal.
The ready signal, in accordance with the setup time standard, must be reached before a predetermined time the clock in synchronism with the CPU 1 rises up (or falls down). Hence, the CPU 1 can stably fetch the ready signal.
However, when the bus master is the CPU 1, the transmission route of ready signal is the route I, and when the bus master is the cache 2, that is the route II. Therefore, the timing of generating the ready signal must be changed depending upon which is the bus master, thereby causing various difficulties in design. Since the CPU 1 in synchronism with an internal clock fetches the signal (the ready signal included), when the ready signal, which passes through the cache 2, delays and is fetched into the CPU 1 for the next clock cycle period, the problem occurs in that the performance of the system is deteriorated.
On the other hand, it is possible to reduce a pass time of the signal through the cache 2, which is not practical because the reduction of time is limited when the clock frequency of the entire system becomes extremely high. Furthermore, there is the problem in that the time is different depending upon whether address decided by the CPU 1 is transmitted through the route I or through the route II.
The aforesaid conventional cache system, when the system is designed, must carry out the timing design and circuit design regarding two cases of the routes I and II, which makes the system design difficult. Also, the system design is difficult also when the timing regulation of the CPU 1 is different from that of the cache 2, either of which being the bus master.